The present invention relates to a synchronization circuit and a synchronization method; and more particularly, the invention relates, for example, to a technique which can be effectively utilized for effecting phase synchronization in a DLL (or PLL) circuit of the type provided in a semiconductor integrated circuit device.
An example of a PLL circuit which can continuously change over between coarse adjustment and fine adjustment is disclosed in Japanese Published Unexamined Patent Application No. Hei 08(1996)-307254. Moreover, an example of a frequency multiplying circuit, including a combining circuit, is disclosed in Japanese Published Unexamined Patent Application No. 11(1999)-004145.
[Patent Document 1]                Japanese Published Unexamined Patent Application No. Hei 08(1996)-307254        
[Patent Document 2]                Japanese Published Unexamined Patent Application No. Hei 11(1999)-004145        